This disclosure relates to circuit reset, and more particularly, relates to structures and techniques allowing for the proper reset of a circuit (or portions thereof) that operate according to a divided clock signal.
In an integrated circuit (IC), different portions may operate at different clock frequencies. For example, a clock divider may be used to “divide down” a given clock signal, and while one part of an IC may operate according to a higher rate clock, one or more other parts of the IC may operate at a lower frequency.
Ensuring that a clock signal reaches different portions of an IC at the same time (ensuring synchronicity) may be a complex task. If lower speed divided clock signals are used for part of an IC, there may be a further increase in design, test, and manufacturing costs to ensure that a divided clock signal (e.g., emanating from a single source) would arrive at different IC locations at roughly the same time. Further, during reset, a clock divider may stop functioning. This could cause lower speed portions of an IC to receive a non-divided (high speed) clock signal, or no clock signal at all.